View V53C318165A_13715.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MOSEL VITELIC
V53C318165A 3.3 VOLT 1M X 16 EDO PAGE MODE CMOS DYNAMIC RAM
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
50
50 ns 25 ns 20 ns 84 ns
60
60 ns 30 ns 25 ns 104 ns
70
70 ns 35 ns 30 ns 124 ns
Features
s 1M x 16-bit organization s EDO Page Mode for a sustained data rate of 50 MHz s RAS access time: 50, 60, 70 ns s Dual CAS Inputs s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh, and Self Refresh. s Refresh Interval: 1024 cycles/16 ms s Available in 42-pin 400 mil SOJ and 50/44-pin 400 mil TSOP-II s Single +3.3 V 0.3 V Power Supply s TTL Interface
Description
The V53C318165A is a 1048576 x 16 bit highperformance CMOS dynamic random access memory. The V53C318165A offers Page mode operation with Extended Data Output. The V53C318165A has an symmetric address, 10-bit row and 10-bit column. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 1024 x 16 bits, within a page, with cycle times as short as 20ns. These features make the V53C318165A ideally suited for a wide variety of high performance computer systems and peripheral applications.
Device Usage Chart
Operating Temperature Range
0C to 70 C
Package Outline K
*
Access Time (ns) 50
*
Power 70
*
T
*
60
*
Std.
*
Temperature Mark
Blank
V53C318165A Rev. 1.0 January 1998
1
MOSEL VITELIC
42-Pin Plastic SOJ PIN CONFIGURATION Top View
VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 NC NC WE RAS NC NC A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
311816500-02
V53C318165A
50/44-Pin Plastic TSOP-II PIN CONFIGURATION Top View
VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 NC
1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40
VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 NC
NC NC WE RAS NC NC A0 A1 A2 A3 VCC
15 16 17 18 19 20 21 22 23 24 25
36 35 34 33 32 31 30 29 28 27 26
311816500-03
NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
Pin Names
A0-A9 RAS UCAS LCAS WE OE I/O1-I/O16 VCC VSS NC Row, Column Address Inputs Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable Data Input, Output +3.3V Supply 0V Supply No Connect
Description SOJ TSOP-II
Pkg. K T
Pin Count 42 50
V53C318165A Rev. 1.0 January 1998
2
MOSEL VITELIC
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70 C Storage temperature range ............... -55 to 150 C Soldering temperature ..................................260 C Soldering time...................................................10 s Input/output voltage .... -0.5 to min (VCC+0.5, 4.6) V Power supply voltage ........................-0.5V to 4.6 V Power dissipation .......................................... 0.5 W Data out current (short circuit) ...................... 50 mA
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
V53C318165A
Capacitance*
Symbol CIN1 CIN2 COUT
TA = 25C, VCC = 3.3 V 0.3 V, VSS = 0 V, f = 1 MHz
Parameter Address Input RAS, UCAS, LCAS, WE, OE Data Input/Output Min. -- -- -- Max. 5 7 7 Unit pF pF pF
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
1024 x 16
OE WE UCAS LCAS RAS
RAS CLOCK GENERATOR
CAS CLOCK GENERATOR
WE CLOCK GENERATOR
OE CLOCK GENERATOR
VCC VSS
DATA I/O BUS COLUMN DECODERS
Y0-Y9
I/O 1 I/O2 I/O3 I/O4 I/O 5 I/O6 I/O7
SENSE AMPLIFIERS REFRESH COUNTER
1024 x 16 12 A0 A1
I/O BUFFER
I/O8 I/O 9 I/O10 I/O11
ADDRESS BUFFERS AND PREDECODERS
ROW DECODERS
X0- X9
1024
* * *
A8 A9
MEMORY ARRAY 1024 x 1024 x 16
I/O12 I/O 13 I/O14 I/O15 I/O16
311816500-04
V53C318165A Rev. 1.0 January 1998
3
MOSEL VITELIC
DC and Operating Characteristics (1-2) TA = 0C to 70C, VCC = 3.3 V 0.3 V, VSS = 0 V, tT = 2ns, unless otherwise specified.
Symbol
ILI ILO ICC1
V53C318165A
Parameter
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating
Access Time
V53C318165A Min.
-10
Typ.
Max.
10
Unit
A A mA
Test Conditions
VSS VIN VCC + 0.3V VSS VOUT VCC + 0.3V RAS, CAS at VIH tRC = tRC (min.)
Notes
1
-10
10
1
50 60 70
200 180 160 2
2, 3, 4
ICC2 ICC3
VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh 50 60 70
mA
RAS, CAS at VIH other inputs VSS tRC = tRC (min.) 2, 4
200 180 160 90 75 60 1.0
mA
ICC4
VCC Supply Current, EDO Page Mode Operation
50 60 70
mA
Minimum Cycle
2, 3, 4
ICC5 ICC6
VCC Supply Current, CMOS Standby Average Self Refresh Current CBR cycle with tRAS > tRASS min., (L-version only) CAS held low, WE = VCC - 0.2V, Address and DIN = VCC - 0.2V or 0.2V VCC Supply Current, during CAS-before-RAS Refresh 50 60 70
mA
RAS VCC - 0.2 V, CAS VCC - 0.2 V
1
1.0
mA
ICC7
200 180 160 -0.5 2 0.8 VCC+0.5 0.4 2.4
mA
tRC = tRC (min)
2, 4
VIL VIH VOL VOH
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
V V V V IOL = 2 mA IOH = -2 mA
1 1 1 1
V53C318165A Rev. 1.0 January 1998
4
MOSEL VITELIC
TA = 0C to 70C, VCC = 3.3 V 0.3 V, VSS = 0V, tT = 2ns unless otherwise noted
JEDEC Symbol Symbol
tRL1RH1 tRL2RL2 tRH2RL2 tRL1CH1 tCL1CH1 tRL1CL1 tWH2CL2 tAVRL2 tRL1AX tAVCL2 tCL1AX tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH
V53C318165A
AC Characteristics
50 Parameter
RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS Output Hold after CAS LOW Access Time from OE Access Time from CAS Access Time from RAS Access Time from Column Address CAS to Low-Z Output Output Buffer Turnoff Delay Data to CAS Low Delay RAS to Column Address Delay Time Output Buffer Turnoff Delay from OE Write Command to CAS Lead Time Write Command Setup Time Write Command Hold Time Write Pulse Width Data to OE Delay Write Command to RAS Lead Time Data in Setup Time 0 0 0 10 0 13 0 8 8 0 13 0 25 13 13
60
70
#
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Min. Max. Min. Max. Min. Max. Unit Notes
50 84 30 40 8 12 0 0 8 0 8 13 5 0 10K 37 10K 60 104 40 50 10 14 0 0 10 0 10 15 5 0 10K 45 10K 70 124 50 60 12 14 0 0 10 0 12 17 5 0 10K 53 10K ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9
tCL1RH1(R) tRSH tCH2RL2 tCH2WX tRH2WX tCL1 tGL1QV tCL1QV tRL1QV tAVQV tCL1QX tCH2QX tCL1QZ tRL1AV tGL2QZ tWL1CH1 tWL1CL2 tCL1WH1 tWL1WH1 tGL1QZ tWL1RH1 tDVWL2 tCRP tRCH tRRH tCOH tOAC tCAC tRAC tCAA tCLZ tOFF tDZC tRAD tOEZ tCWL tWCS tWCH tWP tDEO tRWL tDS
15
0
0
0
ns
9
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
5 13 13 50 25
5 15 15 60 30 0 0 0 12 0 15 0 10 10 0 15 0 30 15 15
5 17 17 70 35 0 0 0 12 0 17 0 10 10 0 17 0 35 17 17
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 15 11 8 15 7, 12 7, 12 7, 13 7
V53C318165A Rev. 1.0 January 1998
5
MOSEL VITELIC
AC Characteristics (Cont'd)
#
33 34 35 36
V53C318165A
JEDEC Symbol Symbol
tWL1DX tWL1GL2 tCH2RH2 tRL2RL2 (RMW) tCL1WL2 tRL1WL2 tAVWL2 tCL2CL2 tCH2CL2 tAVRH1 tCH2QV tCL1RL2 tRH2CL2 tRL1CH1 tRH2CL2 tRH2CL2 tRH2CL2 tRH2CL2 tRH2CL2 tRH2CL2 tRH2CL2 tRH2CL2 tT tDH tWOH tPRWC tRWC tCWD tRWD tAWD tPC tCP tCAR tCAP tCSR tRPC tCHR tRASP tRHCP tCPWD tCPT tWRP tWRH tCDD tODD tT tREF
50 Parameter
Data in Hold Time Write to OE Hold Time EDO Page Mode Read-Write Cycle Time Read-Modify-Write Cycle Time
60
70
Min. Max. Min. Max. Min. Max. Unit Notes
8 10 58 113 10 13 68 138 12 15 77 162 ns ns ns ns 10 10
38 39
CAS to WE Delay RAS to WE Delay in Read-Modify-Write Cycle Column Address to WE Delay EDO Page Mode Read or Write Cycle Time CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge CAS Setup Time CAS-before-RAS Refresh RAS to CAS Precharge Time CAS Hold Time CAS-before-RAS Refresh RAS Pulse Width (EDO Mode) CAS Precharge Time to RAS Delay CAS Precharge Time to WE CAS Precharge Time (CBR Counter Test) Write to RAS Precharge time (CRB Cycle) Write Hold time reference to RAS (CRB Cycle) CAS High to Data delay OE High to Data delay Transition Time (Rise and Fall) Refresh Interval (1024 Cycles)
27 64
32 77
36 89
ns ns
10 10
40 41 42 43 44 46
39 20 8 25 27 10
47 25 10 30 32 10
54 30 10 35 37 10
ns ns ns ns ns ns
10
6
47 48 50 51 52 53 54 55
5 10 50 27 41 35 10 10 200K
5 10 60 32 49 40 10 10 200K
5 10 70 37 56 40 10 10 200K
ns ns ns ns ns ns ns ns
56 57 58 59
10 10 1 50 16
13 13 1 50 16
15 15 1 50 16
ns ns ns ms
16 16
Self Refresh AC Characteristics
60 61 62 tRASS tRPS tCHS RAS Pulse Width During Self Refresh RAS Precharge Time During Self Refresh CAS Hold Time Width During Self Rerfresh 100K 95 50 100K 110 50 100K 130 50 ns ns ns 17 17 17
V53C318165A Rev. 1.0 January 1998
6
MOSEL VITELIC
Notes:
1. All voltage are referenced to VSS. 2. ICC1, ICC3, ICC4, and ICC7 depend on cycle rate. 3. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
V53C318165A
4. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during an EDO cycle (tHPC). 5. An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 7. Measured with a load equivalent to 2 TTL gates and 50 pF (VOL = 0.8V and VOH = 2.0V). 8. tOFF (max.) and tOEZ (max.) define the time at which the outputs acheive the open-circuit condition and are not referenced to output voltage levels. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 11. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain opencircuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.), and tCPWD > tCPWD (min.), the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 12. Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: if tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 13. Operation within the tRAD (max) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: if tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA. 14. AC measurements assume tT = 2 ns. 15. Either tDZC or tDEO must be satisfied. 16. Either tCDD or tODD must be satisfied. 17. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR - Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. 18. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
V53C318165A Rev. 1.0 January 1998
7
MOSEL VITELIC
Waveforms of Read Cycle
tRC tRAS RAS VIH VIL tCSH tCRP UCAS, LCAS VIH VIL tASR ADDRESS VIH VIL ROW ADDRESS tRAD tRAH tASC COLUMN ADDRESS tCAR tRCS WE VIH VIL tCAA tOAC tRRH tCAH tRCD tRSH tCAS tAR tRP
V53C318165A
tCRP
tRCH
OE
VIH VIL tDZC
tCAC tRAC tDZO I/O VOH VOL tLZ tOFZ VALID DATA-OUT
tCDD tOFF
VALID DATA-IN
311816500-05
Waveforms of Early Write Cycle
tRC tRAS VIH RAS VIL tCRP UCAS, LCAS VIH VIL tRAH tASR ADDRESS VIH VIL ROW ADDRESS tRAD tCWL tWP WE VIH VIL tWCR tRWL OE VIH VIL tDHR tDS I/O VIH VIL tDH VALID DATA-IN HIGH-Z
311816500-06
tRP
tAR
t CSH (4) t RCD (6)
tRSH tCAS
tCRP
tCAR tCAH tASC COLUMN ADDRESS tWCH
Don't Care
V53C318165A Rev. 1.0 January 1998
Undefined
8
MOSEL VITELIC
Waveforms of Write Cycle (OE Controlled Write)
tRC tRAS VIH RAS VIL tCSH tCRP UCAS, LCAS VIH VIL tRAD tRAH tASR ADDRESS VIH VIL ROW ADDRESS tASC COLUMN ADDRESS tCWL tRWL tWP WE VIH VIL tWOH OE VIH VIL tOED tDS I/O VIH VIL VALID DATA-IN tDH tCAR tCAH tRCD tRSH tCAS tAR tRP
V53C318165A
tCRP
ROW ADDRESS
311816500-07
Waveforms of Read-Modify-Write Cycle
tRWC tRAS VIH RAS VIL tCSH tCRP UCAS, LCAS VIH VIL tRAH tASR ADDRESS VIH VIL ROW ADDRESS tRAD tASC COLUMN ADDRESS tAWD tCWD tRWD tDZO tCAA tOAC tCWL tRWL tWP ROW ADDRESS tCAH tRCD tRSH tCAS tCRP tAR tRP
WE
VIH VIL
OE
VIH VIL tDZC tCAC tRAC VIH VIL VOH VOL tLZ tOED tOEZ tDS VALID DATA-OUT VALID DATA-IN
311816500-08
tDH
I/O
Don't Care
V53C318165A Rev. 1.0 January 1998
Undefined
9
MOSEL VITELIC
Waveforms of EDO Page Mode Read Cycle
tRASP RAS VIH VIL tRCD tCRP UCAS, LCAS VIH VIL tCSH tASR ADDRESS VIH VIL ROW ADDRESS tRCS WE VIH VIL tCAA tOAC OE VIH VIL tHZ tRAC tCAC tCLZ tOEZ tCOH I/O VOH VOL VALID DATA OUT VALID DATA OUT tOEZ tCAC tLZ tCAC tCAP tOAC tCAA tOAC tRAH tASC COLUMN ADDRESS tRCH tCAH COLUMN ADDRESS tRCS tASC tCAH COLUMN ADDRESS tRCS tCAR tCAS tPC tCP tCAS tRHCP tRSH(R) tCAS tAR
V53C318165A
tRP
tCRP
tCAH
tRCH
tRRH
tOFF tOEZ
VALID DATA OUT
311816500-09
Waveforms of EDO Page Mode Write Cycle
tAR RAS VIH VIL tCRP tRCD UCAS, LCAS VIH VIL tCSH tRAH tASC tRAH ADDRESS VIH VIL tRAD tWCS tWP WE VIH VIL VIH VIL tDS tDS I/O VIH VIL
VALID DATA IN ROW ADD COLUMN ADDRESS
tRP tRASP
tPC tCP tCAS tCAS
tRSH tCRP tCAS
tCAR tASC tCAH
COLUMN ADDRESS COLUMN ADDRESS
tCAH
tCAH
tCWL tWCS tWCH
tCWL tWCS tWCH tWP
tCWL tRWL tWCH tWP
OE
tDS tDH tDH
VALID DATA IN OPEN
311816500-10
tDH
OPEN VALID DATA IN
Don't Care
V53C318165A Rev. 1.0 January 1998
Undefined
10
MOSEL VITELIC
Waveforms of EDO Page Mode Read-Modify-Write Cycle
RAS VIH VIL tCSH tRCD tPCM tCP VIH UCAS, LCAS VIL tCAS tRAD tRAH tASC tASR ADDRESS VIH VIL
ROW ADD COLUMN ADDRESS
V53C318165A
tRASP
tRP tRSH tCRP tCAS tCAS
tCAS tASC tCAH
COLUMN ADDRESS
tASC tCAH
COLUMN ADDRESS
tCAH
tCPWD tRWD tRCS tRWD VIH WE VIL tAWD tCAA tOAC OE VIH VIL tCAP tCAA tODD tCAC tRAC tOEZ tDS I/O VI/OH VI/OL tLZ
OUT IN OUT
tCWD tCWL tCWL
tCWD tCWL
tRWL
tAWD tWP tOAC tWP tOAC
tAWD tWP
tCAP tCAA tODD tODD tCAC tOEZ tOEZ tDH tDS
IN OUT
tCAC tDH
tDH tDS
IN
311816500-11
tLZ
tLZ
Waveforms of RAS Only Refresh Cycle
tRC tRP RAS VIH VIL tCRP UCAS, LCAS VIH VIL tASR ADDRESS VIH VIL ROW ADDR tRAH tRAS
I/O
VOH VOL NOTE: WE, OE = Don't care
HIGH-Z
311816500-12
Don't Care
V53C318165A Rev. 1.0 January 1998
Undefined
11
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
tRAS RAS VIH VIL tCHR tCSR VIH UCAS, LCAS VIL VIH VIL tCP tRSH tCAS
V53C318165A
tRP
ADDRESS
READ CYCLE WE VIH VIL tWRH
tWRP
tRCS
tRRH tRCH
tOAC OE VIH VIL tLZ I/O VIH VIL tRWL tCWL tWRP WE VIH VIL tWRH OE VIH VIL tDS I/O VIH VIL D IN
311816500-13
tCHZ tOEZ DOUT
WRITE CYCLE
tWCS
tWCH
tDH
Waveforms of CAS-before-RAS Refresh Cycle
tRP RAS VIH VIL tCP tCSR UCAS, LCAS VIH VIL tOFF I/O VOH VOL NOTE: WE, OE, A0-A9 = Don't care
311816500-14
tRC tRAS
tRP
tRPC tCHR
Don't Care
V53C318165A Rev. 1.0 January 1998
Undefined
12
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
tRC VIH VIL tRCD tCRP UCAS, LCAS VIH VIL tASR tRAH ADDRESS VIH VIL
ROW ADD COLUMN ADDRESS
V53C318165A
tRC tRP tRAS tRP
tRAS tAR
RAS
tRSH(R)
tCHR
tCRP
tRAD tASC tCAH
tRCS WE VIH VIL tCAA tOAC OE VIH VIL tCAC tLZ tRAC VOH I/O VOL
tRRH
tCHZ tOEZ
VALID DATA
311816500-15
Waveforms of Hidden Refresh Cycle (Write)
tRC VIH RAS VIL tRCD tCRP VIH UCAS, LCAS VIL tASR tRAH ADDRESS VIH VIL
ROW ADD COLUMN ADDRESS
tRC tRP tRAS tRP
tRAS tAR
tRSH(R)
tCHR
tCRP
tRAD tASC tCAH
tWCS WE VIH VIL
tWCH
OE
VIH VIL tDS VIH tDH
VALID DATA-IN
I/O
VIL
tDHR
311816500-16
Don't Care
V53C318165A Rev. 1.0 January 1998
Undefined
13
MOSEL VITELIC
Waveforms of Self Refresh Cycle (optional)
tRP RAS VIH VIL tRPC tCSR tCP UCAS, LCAS VIH VIL VIH VIL tCHS tRPC tRASS tRPS
V53C318165A
ADDRESS
I/O
VOH VOL
OPEN
WE
VIH VIL
OE
VIH VIL
311816500-17
Don't Care
Undefined
Functional Description
The V53C318165A is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C318165A reads and writes data by multiplexing an 20-bit address into a 10-bit row and a 10-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address "flows through" an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time.
Read Cycle
A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC, tRAC, tCAA and tCAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied.
Memory Cycle
A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP/tCP has elapsed.
V53C318165A Rev. 1.0 January 1998
14
MOSEL VITELIC
Extended Data Output Page Mode
EDO Page operation permits all 1024 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer. During EDO operation, Read, Write, Read-Modify-Write or Read-WriteRead cycles are possible at random addresses within a row. Following the initial entry cycle into EDO Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA. In both cases, the falling edge of CAS latches the address and enables the output. EDO provides a sustained data rate of 50 MHz for applications that require high bandwidth such as bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 1024 Data Rate = ------------------------------------------t RC + 1023 x t PC
V53C318165A
The Self Refresh mode is terminated by returning the RAS clock to a high level for a specified (tRPS) minimum time. After termination of the Self Refresh cycle normal accesses to the device may be initiated immediately, poviding that subsequest refresh cycles utilize the CAS before RAS (CBR) mode of operation.
Data Output Operation
The V53C318165A Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE signal has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied.
Power-On
After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C318165A is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and ICC will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
Self Refresh
Self Refresh mode provides internal refresh control signals to the DRAM during extended periods of inactivity. Device operation in this mode provides additional power savings and design ease by elimination of external refresh control signals. Self Refresh mode is initialed with a CAS before RAS (CBR) Refresh cycle, holding both RAS low (tRASS) and CAS low (tCHD) for a specified period. Both of these parameters are specified with minimum values to guarantee entry into Self Refresh operation. Once the device has been placed in to Self Refresh mode the CAS clock is no longer required to maintain Self Refresh operation.
V53C318165A Rev. 1.0 January 1998
15
MOSEL VITELIC
Table 1. V53C318165A Data Output
Operation for Various Cycle Types
Cycle Type
Read Cycles CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles EDO Read Cycle EDO Write Cycle (Early Write) EDO Read-Modify-Write Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle CAS-only Cycles
V53C318165A
I/O State
Data from Addressed Memory Cell High-Z OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z Data from Addressed Memory Cell High-Z High-Z High-Z
V53C318165A Rev. 1.0 January 1998
16
MOSEL VITELIC
Package Diagrams
42-Pin 400 mil SOJ
1.08 -0.010 [27.41 -0.25] 42 22 .441 -0.006 [11.2 -0.15](1) 0.3700.010 [9.40.25] .441 0.006 [11.2 0.15]
V53C318165A
.406 -0.012 [10.3 -0.3]
1
21 0.045 [1.15] MIN
.406 -0.012(1) [10.3 - 0.3]
0.008 -0.002
0.088 0.004 [2.24 0.1]
+0.005 +0.12
0.2 -0.05
0.81 [.032] MAX
0.0170.004 [0.43 0.1] 0.05 [1.27] 1.0 [25.4]
0.145 [3.68] MAX
0.004 [0.1]
Unit in inches [mm]
(1) Does not include plastic or metal protrusion of 0.010 [0.25] max per side.
50/44-Pin 400 mil TSOP-II
0.039 0.002 [1 0.05] 0.0040.002 [0.10.05] 0.047 Max [1.2 Max] 0.4 0.005 [10.16 0.13] 0.006 -0.001
+0.08 0.15 -0.03 +0.003
0.031 [0.8] 0.016 +0.002 -0.004 0.4 +0.05 -0.1 50 40 36 26 0.008 [0.2] M 44x
0.004 [0.1]
0.0200.004 [0.5 0.1] 0.4630.008 [11.76 0.2]
1
11
15
1
25 Unit in inches [mm]
0.8250.005 [20.950.13]
1
Does not include plastic or metal protrusion of 0.010 [0.25] max. per side
V53C318165A Rev. 1.0 January 1998
17
MOSEL VITELIC
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 011-886-2-545-1213 FAX: 011-886-2-545-1209 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 011-886-35-783344 FAX: 011-886-35-792838
V53C318165A
JAPAN
WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 011-81-43-299-6000 FAX: 011-81-43-299-6555
HONG KONG
19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 011-852-665-4883 FAX: 011-852-664-7535
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185
SOUTHWESTERN
SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174
CENTRAL & SOUTHEASTERN
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341
NORTHEASTERN
SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347
(c) Copyright 1998, MOSEL VITELIC Inc.
1/98 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

▲Up To Search▲

Price & Availability of V53C318165A

	To Download V53C318165A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .